The present invention is bit synchronizing method and bit synchronizer for Gaussian filtering minimum deviation keying demodulation circuit. The synchronizing method includes the equispaced sampling to input signal, cross zero level corresponding with digital number Vmean, Nstd=f1/f2, Nref recording the present sampled number; one counter N used to record the sample number within one bit being increased by 1 after each sample and reset for the sample of the next bit in finishing one bit; comparing N with Nref in finishing each sampling and finishing the present bit when N is not smaller than Nref or comparing Vsamp and Vmean in other case; comparing N and Nstd/2 when Vsamp=Vmean, regulating the present bit needed sample number to Nref=Nstd-1 when N is not smaller than Nref/2, or else to Nref=Nstd+1. |