This invention provides a clock signal generator. The phase lock loop circuit is composed of a phase comparator 13, a differential amplifier 14, a low-pass filter 15, and a voltage controlled oscillation circuit(VCO) 16, and is controlled so that an output signal SPB of a detecting circuit 12 and a clock signal CLK are phase-locked. A error amount integration circuit 21 integrates the error occurrence amount in an error correction circuit 17, and a microcomputer 22 sets a reference voltage data DVREF according to the integrated error amount ERR. The reference voltage data DVREF is converted into a reference voltage VREF, and the working point of the VCO 16 is controlled by the reference voltage VREF. |