A test circuit comprises a delay circuit 11 with controllable delay, a phase comparator circuit 12 for comparing the phases between the clock signal S0 and a delay clock signal S1 delayed from the clock signal S0 by the delay circuit 11, a meas counter 13 for counting the number of outputs of the prescribed comparison result from the phase comparator circuit 12, a signal switching circuit 14 for switching an input signal to the delay circuit 11 from the clock signal S0 to a delay signal satisfying an oscillation condition where the delay signal is received from the delay circuit 11 and developing a ring oscillator, and a frequency measuring circuit 15 for measuring an oscillation frequency when the ring oscillator is developed, the delay circuit 11 includes a variable delay circuit 17 with variable delay units connected to control the delay in each variable delay units independently. |